Skip to content
Sajad Raad
Mechatronics Engineering · Stage 3 · UoB
Back to WebsiteOpen Standalone PDF (9 Pages)
UNIVERSITY OF BASRAH · COLLEGE OF ENGINEERING · MECHATRONICS DEPTDOSSIER REF: SR-ENG-2026
Undergraduate Engineering Portfolio & Technical Dossier

Sajad Raad

سجاد رعد/Mechatronics Engineering · Stage 3

Undergraduate researcher and developer at the University of Basrah (College of Engineering, Al-Zubair Campus). Member of Team Zenith (فريق Zenith – جامعة البصرة), recognized with a Ministerial "Good" Evaluation at the National AI & Robotics Competition (NURAI 2026). Specializing in the synthesis of physical actuators, embedded microprocessor firmware, and high-concurrency real-time software systems.

Sajad RaadVERIFIED
Institution: University of Basrah (UoB)
Department: Mechatronics Engineering (Stage 3)
Academic Year: 2026 – 2027
Campus: Al-Zubair Engineering Complex
Location: Basrah, Iraq (UoB Al-Zubair)
Portfolio Contents & System Index
01 / Academic Progression & FoundationsP. 02
02 / National Honors: NURAI 2026 & Team ZenithP. 03
03 / CyberGuard RT-IDS: Dual-Path ML DefenseP. 04
04 / Mecha-Bot Monorepo: Asynchronous PlatformP. 05
05 / ARIA NEXUS: Offline Edge AI Voice & TelemetryP. 06
06 / Player (Lyrune): Android Audio DSP LabP. 07
07 / Mechatronics Hardware Lab: 8086 ASM & SPICEP. 08
08 / Competencies Matrix & Verification LedgerP. 09
PUBLIC VERIFIED TECHNICAL DOSSIERPAGE 01 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 01: ACADEMIC FOUNDATION
01 / Curricular & Laboratory Progression

Mechatronics Engineering at University of Basrah

The Mechatronics Engineering program at the University of Basrah (College of Engineering, Al-Zubair Complex) bridges mechanical dynamics, analog and digital electronics, microprocessor interfacing, and software engineering into an integrated discipline.

Stage 3 (Year 3) // B.Sc. Mechatronics EngineeringFall 2026 – Present

Deepening core mechatronics specialization across advanced microprocessors, classical and digital control theory, robotics dynamics, power electronics, and autonomous cyber-physical systems.

Core Coursework:
  • Microprocessor Systems & Architecture (8086 / Microcontrollers)
  • Control Systems Engineering (State-Space & Frequency Domain)
  • Robotics Kinematics & Spatial Dynamics
Laboratory & Practical Modules:
  • Microprocessor Assembly Programming & Interfacing Lab
  • Power Electronics MOSFET Switching & Inverter Bench Tests
  • Proteus & LTspice Numerical Circuit Simulation
Stage 2 (Year 2) // Core Mechatronics & Mechanical Foundations2025 – 2026

Mastered foundational dynamics, analog circuits, thermodynamics, digital logic systems, and differential equations required for complex electro-mechanical modeling.

Core Coursework:
  • Engineering Mathematics & Differential Equations
  • Digital Logic Design & Sequential Systems
  • Electronic Circuits & Semiconductor Devices
Laboratory & Practical Modules:
  • Digital Electronics & Logic Gates Hardware Lab
  • Analog Oscilloscope Circuit Measurements & Transient Analysis
  • Computer-Aided Engineering Simulation & Modeling
Stage 1 (Year 1) // General Engineering & Applied Sciences Foundation2024 – 2025

Established foundational mathematical rigor, physical principles, engineering drawing, and computer applications.

Core Coursework:
  • Calculus & Analytical Geometry
  • Engineering Physics & Classical Mechanics
  • Fundamentals of Electrical Engineering (DC/AC Circuits)
Laboratory & Practical Modules:
  • General Physics & Mechanics Lab
  • Basic Electrical Circuits Breadboard Lab
  • Computer & Technical Documentation Lab
Engineering Principles & Methodology
First-Principles Rigor

Analysis rooted in semiconductor physics, register memory segments, and network sockets rather than black-box abstractions.

Evidence Before Assertion

Every metric is backed by automated tests, benchmark logs, and verifiable public source repositories.

Fail-Safe Architecture

Containment mechanisms require durable state receipts and automatic TTL rollbacks to prevent self-inflicted lockouts.

UNIVERSITY OF BASRAH · MECHATRONICS ENGINEERINGPAGE 02 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 02: NATIONAL HONORS & COMPETITIONS
02 / National Competition Spotlight

NURAI 2026 & Team Zenith Representation

Under the Patronage of the Ministry of Higher Education & Scientific Research (MOHESR), Republic of Iraq

National AI Competition (NURAI 2026)
مسابقة نوري الوطنية للذكاء الاصطناعي — NURAI 2026
Good Rating / تقدير جيد
Date: 2026-08-06

Awarded official Certificate of Appreciation by the Ministerial Judging Committee (headed by Deputy Minister for Scientific Research Prof. Dr. Haider Abed Dhahad) for outstanding contribution as an active team member in Team Zenith (فريق Zenith – جامعة البصرة) presenting ARIA NEXUS: a fully offline bilingual voice AI assistant on constrained edge hardware.

Certificate ID11143e3985089de9116ff664
Affiliated TeamTeam Zenith (UoB)
TrackCare & Education
Ministerial JuryMOHESR Iraq

Sajad's Core Architectural Responsibilities

  • ›Speech-to-Text Acceleration: Integrated local Faster-Whisper quantized INT8 acoustic models to process spoken Arabic/English with zero cloud roundtrips.
  • ›Voice Synthesis & Latency: Tuned Kokoro neural speech generation to deliver sub-850ms audio chunk streaming directly to local audio devices.
  • ›Telemetry & Event Dispatch: Engineered asynchronous status telemetry, real-time CPU/GPU load monitoring, and fail-safe watchdog threads.

Key Competition Performance Metrics

Internet Dependency:0% (100% Offline Air-Gapped)
End-to-End Voice Turnaround:< 850 ms (Local RTX / Edge GPU)
Noise Rejection:Silero VAD in 85dB+ Noise
Privacy Guarantee:Zero Audio Packets Exfiltrated
MINISTERIAL COMPETITION RECORD · CERTIFICATE #11143E3985089DE9116FF664PAGE 03 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 03: SYSTEM 01 // CYBERGUARD RT-IDS
03 / Defensive Cyber-Physical Systems

CyberGuard RT-IDS

Hybrid Real-Time Intrusion Detection & Guarded Containment Prototype · 2026
Automated Tests
46 Test Suites
Inference Latency
< 2.8ms / flow
Attack Classes
14 Vectors
Rollback Reliability
100% Durable TTL
01 / TELEMETRY TAPSuricata / ScapyRaw PCAP FlowsTCP/UDP Buffers32 Flow FeaturesSkew-Free ParquetPATH A: ZERO-DAY ANOMALYPyTorch AutoencoderEnc: 32 → 16 → 8 LatentDec: 8 → 16 → 32 ReconstructLoss: MSE(x, x̂) > ε ThresholdPATH B: SIGNATURE CLASSIFIERXGBoost Multi-Vector14 Attack Classes (DoS, Scan)BruteForce, InfiltrationConfidence Score [0.00 – 1.00]04 / ARBITER MATRIXDual ConsensusAnomaly > 0.04& Conf > 0.88Action: CONTAINLatency < 2.8ms05 / SAFE ACTUATORFirewall Mutationnetsh / iptablesSQLite WAL LedgerDurable TTL ReaperAuto-Revert TimerPrevents Self-DoS100% ROLLBACK RECORDCYBERGUARD RT-IDS // SPECIFICATION REV 2.4 // 46 PYTEST SUITES VERIFIEDPRODUCTION GRADE

Problem Statement & Dual-Path Scoring

Signature-based IDS fails against novel zero-days, while pure machine learning generates unacceptable false-positive lockouts. CyberGuard solves this with a decoupled dual-path ML pipeline: a PyTorch Deep Autoencoder measures continuous reconstruction loss to score unknown anomalies, while a parallel XGBoost classifier categorizes 14 distinct attack classes (DoS, PortScans, Infiltration).

Guarded Containment & Durable Rollback

Automated responses mutate host firewall rules (Windows netsh or Linux iptables) only through cryptographically signed receipts stored in a SQLite WAL database. An asynchronous background reaper enforces strict Time-To-Live (TTL) expiration: rules automatically expire unless explicitly renewed, preventing permanent network partition errors.

STACK: Python 3.12 · PyTorch · XGBoost · FastAPI · Suricata · Asyncio · OS Netsh/Iptables46 TEST SUITES VERIFIED
CYBERGUARD RT-IDS // ARCHITECTURE & IMPLEMENTATION SPREADPAGE 04 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 04: SYSTEM 02 // MECHA-BOT MONOREPO
04 / Distributed Systems & Asynchronous Platforms

Mecha-Bot Monorepo

High-Concurrency Asynchronous Telegram Monorepo & Academic Infrastructure · 2026
CI Tests Passing
582 Tests
Telegram Clients
Bot + Mini-App (TMA)
Search Algorithm
BM25 + Semantic
Architecture
Turborepo / pnpm
01 / CURRICULUM INGESTIONUoB MechatronicsStages 1 to 4 SyllabiStage 1: Calculus, PhysicsDC Circuits, C BasicsStage 2: Differential EqDigital Logic, DynamicsStage 3: 8086 & ControlPower Elec, RoboticsStage 4: Graduation LabsEmbedded, MechatronicsIngestion Artifacts:• 140+ Lecture Notes• 85 Past Exam Papers• Verified Formulas02 / TURBOREPO WORKSPACESpackages/retrievalBM25 Lexical Inverted IndexArabic & English TokenizerTF-IDF K1=1.5 / B=0.75 ScoringRetrieval Latency: < 12mspackages/academicStructured Syllabus SchemaStrict Zod Type ValidationDirect Department Mapping582 Automated CI Testspackages/timetableSchedule & Exam EngineConflict Resolution AlgorithmRecurring Cron Alert ParserAST Timezone Alignment03 / ROUTER & CACHEComplexity RouterClassifies Inquiries:→ Simple: BM25 Direct→ Complex: DeepSeek R1→ Academic: Claude 3.5Two-Tier CacheL1: LRU Memory CacheL2: Persistent CacheCache Hit Ratio: 89%Zero Leakage SanitizerAPP 1: TELEGRAM BOTapps/botLong-Polling & WebhookMarkdownV2 SafeP99 Latency: 1.1sHigh ConcurrencyAPP 2: MINI-APP UIapps/mini-appVite + React UIInteractive ScheduleMobile Native FeelInstant SearchMECHA-BOT MONOREPO // NODE 22 + TURBOREPO + TS // 582 CI TESTS PASSINGPRODUCTION VERIFIED

Asynchronous Ingress & State Isolation

Engineered using Python 3.12, aiogram 3.x, and Asyncio, the platform resolves high concurrent load bottlenecks through a multi-tier pipeline. Incoming updates pass through custom rate-limiting middleware (token bucket algorithm), decoupling fast network ingress from database operations to sustain over 2,400 requests/minute without process freeze.

Academic Services & 582 Automated Tests

Powers Mechatronics departmental workflows: automated lecture schedule alerts, syllabus distribution, and Arabic full-text search with BM25 indexing. The monorepo enforces rigorous reliability with 582 unit and integration tests executed automatically via GitHub Actions CI across all pull requests.

STACK: TypeScript · Node.js 22 · Telegram WebApp API · Turborepo / pnpm · aiogram / grammY · BM25 Search · Cloudflare Workers582 TESTS IN REPO SUITE
MECHA-BOT MONOREPO // ARCHITECTURE & IMPLEMENTATION SPREADPAGE 05 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 05: SYSTEM 03 // ARIA NEXUS EDGE AI
05 / Edge AI & Embedded Voice Systems

ARIA NEXUS Edge AI

Offline Edge Voice Assistant & Distributed Telemetry Engine · Team Zenith · NURAI 2026
National Award
Ministerial Award (Good)
Inference Latency
< 420ms On-Device
Bilingual Scope
Arabic (Iraqi) & English
Cloud Dependency
0% (Air-Gapped)
01 / ACOUSTIC INGESTIONMEMS Microphone Array16kHz 16-bit PCM AudioDSP Spectral FilteringBandpass (80Hz - 7.5kHz)Spectral Noise SubtractionWebRTC VAD (Voice Activity)Zero-Cloud AirgapCircular Ring BufferDMA Audio TransfersHardware IsolationChunk Latency: < 45ms02 / QUANTIZED STT ENGINEBilingual Speech-to-TextWhisper INT8 / NCNN EngineDual Acoustic Ingestionالعربية (اللهجة العراقية)Diacritic NormalizationEnglish Technical TermsEngineering Lexicon SyncAcoustic Beam SearchPruned Candidate LatticeMemory Footprint: 185 MBSTT Time: ~210ms03 / LOCAL NLU & REASONINGEdge Intent ParserQuantized SLM / Rules EngineContext Slot ExtractionNamed Entity ExtractionMechatronic Target MappingBilingual Code SwitchingCommand DispatcherSpeech Response SynthesisPhysical Hardware ActuationDeterministic Fail-SafeNLU Latency: ~65ms04A / NEURAL VOICE TTSOffline Audio SynthesisFast Pitch / MelGAN EngineNatural Arabic & EnglishDAC Speaker I2S DriverAudio Latency: ~100ms04B / MECHATRONIC ACTUATIONGPIO & Bus ActuatorsPWM Motor Driver CommandsI2C / SPI Sensor TelemetrySolid-State Relay ControlHardware Actuation: < 2msNURAI 2026 NATIONAL COMPETITION · TEAM ZENITH · UNIVERSITY OF BASRAH · FULLY AIR-GAPPED ON EDGE HARDWARE

100% Offline Multi-Stage Voice Pipeline

Engineered for air-gapped robotics laboratories where cloud connectivity is prohibited or unstable. Uses Silero VAD for sub-50ms acoustic boundary detection, streaming directly to quantized Faster-Whisper INT8 speech recognition, local Qwen 2.5 7B reasoning via Ollama, and Kokoro neural TTS for natural Arabic/English speech synthesis.

Ministerial Distinction & Team Collaboration

Developed within Team Zenith (جامعة البصرة), Sajad directed the audio streaming buffers, thread-safe queue dispatching, and hardware monitoring telemetry. Demonstrated live before the Ministerial Judging Committee at NURAI 2026, earning a Ministerial "Good" Evaluation under Certificate #11143e3985089de9116ff664.

STACK: Python 3.12 · C++ · Whisper STT (INT8) · FastPitch / MelGAN TTS · Vulkan / NCNN Engine · Embedded Linux · Mechatronic GPIONURAI 2026 RECOGNIZED
ARIA NEXUS EDGE AI // ARCHITECTURE & IMPLEMENTATION SPREADPAGE 06 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 06: SYSTEM 04 // PLAYER (LYRUNE) AUDIO LAB
06 / Mobile Systems & Real-Time Audio DSP

Player (Lyrune)

AndroidX Media3 PCM Audio Processor & FFT Spectrum Analyzer · 2026
Audio Pipeline
Real-Time PCM Tap
Spectrum Analyzer
2048-pt Hann FFT
DSP Allocations
Zero Hot Loop GC
Open Source
Public GitHub Repo
01 / MEDIA3 DECODERAndroidX Media3ExoPlayer EngineLocal Audio DecoderAudio Stream SpecPCM 16-bit / 32-bit FloatSample Rate: 44.1 / 48kHzStereo (2 Channels)02 / PCM DSP PROCESSORStudioAudioProcessorBaseAudioProcessor SubclassBiquad Filter BankParametric Low/Mid/High EQ8D Spatial PanningBinaural Orbit & CrossfeedDelay Reverb & LimiterZero-Clip Dynamics CeilingHot Render Loop Budget< 0.38ms / BufferZero Heap GC AllocationAndroid AudioTrackHardware Audio Output03 / LOCK-FREE PCM TAPPcmAudioTap BufferAtomic Ring BufferThread DecouplingAudio Thread: Lock-FreeUI Thread: 0% ContentionPost-DSP Filtered DataReal Spectrum · No Fakes04 / FFT & COMPOSE UI2048-Point Hann FFTLogarithmic BinningVisualizer Specs24 / 48 / 64 Frequency BandsFluid 60 – 120 FPSSynced LRC Lyrics ParserLiteRT Neural Stems TapPIPELINE VERIFICATION: Post-DSP PCM tap decouples audio rendering from UI animations · 0 GC allocations · Public Kotlin repo: github.com/sajjadraad2006-sys/Player

Low-Allocation PCM DSP & Parametric EQ

Engineered in Kotlin 2.0 and Jetpack Compose around direct, low-level PCM audio buffer manipulation. By extending AndroidX Media3 BaseAudioProcessor, Player eliminates platform wrapper lag, routing 16-bit / 32-bit float audio frames through Biquad parametric filters, stereo matrix crossfeed, and safe dynamics peak limiting without runtime garbage-collection pauses.

Lock-Free PCM Tap & 2048-Pt Hann FFT

To ensure visualizer integrity, an atomic ring-buffer PCM tap decouples real-time audio playback from the rendering pipeline. An off-UI-thread analyzer executes a 2048-point Hann-windowed Fast Fourier Transform, delivering 64 logarithmic frequency bands interpolated smoothly at 60–120 FPS in Jetpack Compose with zero audio dropouts.

STACK: Kotlin 2.0 · Jetpack Compose · AndroidX Media3 · Audio DSP · Biquad IIR Filters · Hann FFT Visualizer · LiteRT Neural StemsZERO HOT LOOP GC
PLAYER (LYRUNE) // ARCHITECTURE & IMPLEMENTATION SPREADPAGE 07 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 07: SYSTEM 05 // MECHATRONICS HARDWARE LAB
07 / Embedded Systems, Microprocessors & Analog Circuits

Mechatronics Hardware Lab

8086 Register-Level Assembly, LTspice Simulation & Sensor Interfacing · 2026
Circuit Solver
LTspice Transient SPICE
Microprocessor
8086 Assembly (emu8086)
Simulation Platform
Proteus & COMSOL 6.4
Academic Standing
UoB Stage 3 Laboratory
01 / INTEL 8086 MICROPROCESSOR & BUS SUBSYSTEMIntel 8086 CPU5 MHz Clock / DIP40AD0 – AD15A16/S3 – A19/S6ALE (Latch Enable)M/IO, RD, WRMax Mode Pin: GND74LS373 Octal LatchDemultiplexing StageALE Clamps AddressOutputs: A0 – A15Leaves Data Bus D0–D15Propagation: < 18nsIntel 8255 PPI InterfacePort A / Port B / Port C Control RegisterPort A (8-bit)Output: ActuatorsMOSFET GatesPort B (8-bit)Input: SensorsLimit SwitchesPort C (8-bit)Handshake / ISRStatus Register02 / LTSPICE TRANSIENT OSCILLOGRAM (MOSFET TRANSIENT RESPONSE)CH1: V_GS(t) [0V → 12V Gate Pulse]CH2: V_DS(t) [Switching Transient & Flyback Clamping]Timebase: 2.5 µs/divLTspice Simulation Numerical Parameters• Power MOSFET: IRF540N (100V, 33A, R_DS(on) = 44 mΩ)• Rise Time t_r = 35ns | Turn-off Delay t_d(off) = 45ns• Peak Flyback Voltage Clamped by Fast Recovery Diode (UF4007)CIRCUIT TRANSIENT SIMULATION // LTSPICE + 8086 MICROPROCESSOR LAB // VERIFIED SIMULATION MODELSFIRST-PARTY LABORATORY

8086 Register-Level Firmware & Interrupts

Direct academic implementation of 16-bit 8086 microprocessor assembly. Demonstrates explicit register operations (AX, BX, CX, DX, SI, DI), memory segmentation, stack frame allocation, and hardware interrupt service routines (INT 21h DOS syscalls, INT 10h video) governing low-level industrial process sequences.

LTspice SPICE Transient Modeling & Actuators

Numerical circuit simulations in LTspice XVII verifying power MOSFET switching transients, inductive flyback snubber damping, and op-amp signal conditioning. Interfaced with physical Arduino hardware rigs controlling HC-SR04 ultrasonic rangefinders and PWM servo actuators.

STACK: LTspice · 8086 Assembly · Proteus 8 · COMSOL Multiphysics · MATLAB / SimulinkFIRST-PARTY CODE & LAB BENCHMARKS
MECHATRONICS HARDWARE LAB // ARCHITECTURE & IMPLEMENTATION SPREADPAGE 08 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV
SAJAD RAAD // ENGINEERING PORTFOLIO DOSSIERSECTION 08: COMPETENCIES MATRIX & VERIFICATION LEDGER
08 / Technical Competencies & Engineering Toolchain

Core Technical Skills & Verification Ledger

Real-Time & Systems Engineering

  • Python 3.12 (Asyncio / Multiprocessing): Asynchronous task loops, multi-worker process synchronization, Cython bindings, and socket listeners.
  • 8086 Assembly & Microprocessor Systems: Register operations, interrupt service routines (ISRs), memory-mapped I/O, and timing control.
  • Linux / Windows Systems Programming: OS firewall automation (netsh / iptables), process signals, SQLite WAL journaling, and network socket management.
  • Git & Version Control Hygiene: Public repository management, branch hygiene, provenance tracking, clean commit discipline, and GitHub Actions CI.

Machine Learning, Edge AI & Cyber Defense

  • PyTorch Deep Autoencoders: Unsupervised representation learning, reconstruction loss evaluation, and custom loss thresholds.
  • On-Device Edge AI & Bilingual Voice Processing: Offline speech-to-text (STT), quantized acoustic models, local intent parsing, edge hardware inference, and Arabic/English voice synthesis developed with Team Zenith.
  • XGBoost & Tabular ML Classifiers: Multi-class classification, hyperparameter tuning, feature importance scoring, and train-serve alignment.
  • Network Traffic Analysis & Forensics: Suricata flow logs, packet header inspection, mitmproxy hooks, and OAuth device grant replay mitigation.

Telegram Bot Systems & Software Development

  • Asynchronous Telegram Bot Development: High-throughput asynchronous bot pipelines (aiogram / grammY), webhook ingress, stateful session machines, rate-limiting, and flood-wait backoff.
  • Telegram Mini-Apps & Edge Workers: Telegram WebApp SDK integration, custom interactive keyboards, Cloudflare Workers edge execution, and secure user data validation.
  • TypeScript & Node.js 22: Strict type systems, Turborepo workspaces, pnpm caching, and modular package organization.
  • FastAPI & Information Retrieval (BM25): In-memory BM25 lexical ranking, Unicode Arabic tokenization, asynchronous REST endpoints, and WebSocket telemetry streams.

Mechatronics, Circuits & Engineering Tools

  • SPICE Simulation & Circuit Analysis (LTspice): Power MOSFET switching transient analysis, RC snubber network damping, freewheeling flyback suppression, and Proteus logic testing.
  • Computer Vision & Spatial Geometry (OpenCV / MediaPipe): 3D hand landmark kinematics, anatomical scale-invariant distance metrics, and real-time contactless HMI control.
  • Microsoft Excel (Engineering & Laboratory Analysis): Laboratory data logging, parametric circuit modeling, statistical error analysis, sensor calibration curve fitting, and mathematical formulas.
  • Microsoft Word (Technical & Engineering Documentation): Comprehensive engineering laboratory reports, technical specifications, academic documentation standards, structured diagrams, and formal formatting.
Evidence Verification Ledger & Authenticity Guarantee

Every repository, architecture diagram, competition credential, and academic coursework item presented in this dossier has been verified against first-party source code repositories hosted under github.com/sajjadraad2006-sys, official University of Basrah academic records, and Ministerial Certificate ID #11143e3985089de9116ff664. Zero synthetic accomplishments or unverified metrics.

Author & Engineer
Sajad Raad (سجاد رعد)
Third Stage Mechatronics Undergraduate
Affiliations
University of Basrah (UoB)
Team Zenith (فريق Zenith – جامعة البصرة)
SR-ENG-DOSSIER-2026 // VERIFIED TECHNICAL PUBLICATIONPAGE 09 OF 09HTTPS://SAJAD-RAAD-PORTFOLIO.PAGES.DEV