Skip to content
Sajad Raad
Mechatronics Engineering · Stage 3 · UoB
Back to Selected Work
CASE STUDY // REF: MECHATRONICS-HARDWARE-LAB·Coursework & Simulation
Embedded & Mechatronics Hardware · Year 2026

Mechatronics Lab & Circuit Simulation Suite

High-Speed Switching Circuits, 8086 Assembly & Multiphysics Analysis

Circuit Solver
LTspice Transient SPICE
Microprocessor
8086 Assembly (emu8086)
Simulation Platform
Proteus & COMSOL 6.4
Academic Standing
UoB Stage 3 Laboratory
LTspice8086 AssemblyProteus 8COMSOL MultiphysicsMATLAB / Simulink
01

Project Overview

This project showcases foundational mechatronics engineering laboratory and simulation coursework developed during Stages 2 and 3 at the University of Basrah. It encompasses transient SPICE circuit analysis of MOSFET switching topologies with RC snubbers, low-level 8086 assembly language programming for microprocessor control, Proteus logic simulation, and COMSOL multiphysics finite element modeling.

02

Problem and Motivation

Mechatronics systems bridge the gap between software algorithms and physical actuators (motors, solenoids, valves). Software commands must ultimately drive power electronics. High-speed switching circuits generate dangerous inductive voltage spikes and thermal transients that destroy microcontroller pins if not properly damped. Mastering circuit dynamics and register-level assembly is non-negotiable for true mechatronics engineering competence.

03

Requirements and Constraints

  • ■Sub-microsecond transient response damping to protect driver gates from inductive kickback.
  • ■Deterministic instruction execution cycle timing on 8086 assembly routines.
  • ■Accurate netlist representation matching physical lab bench testing components.
04

My Role & Contributions

  • ›Calculated RC snubber component values and gate drive resistor limits.
  • ›Simulated transient switching waveforms and flyback diode protection in LTspice.
  • ›Wrote 8086 assembly routines for memory-mapped I/O and interrupt handling.
05

System Architecture

Hierarchical engineering analysis flow from mathematical design to SPICE simulation and microprocessor firmware.

MECHATRONICS LAB HARDWARE & TRANSIENT SCHEMATIC
FIG. 05 // 8086 BUS ARCHITECTURE & MOSFET TRANSIENT
01 / INTEL 8086 MICROPROCESSOR & BUS SUBSYSTEMIntel 8086 CPU5 MHz Clock / DIP40AD0 – AD15A16/S3 – A19/S6ALE (Latch Enable)M/IO, RD, WRMax Mode Pin: GND74LS373 Octal LatchDemultiplexing StageALE Clamps AddressOutputs: A0 – A15Leaves Data Bus D0–D15Propagation: < 18nsIntel 8255 PPI InterfacePort A / Port B / Port C Control RegisterPort A (8-bit)Output: ActuatorsMOSFET GatesPort B (8-bit)Input: SensorsLimit SwitchesPort C (8-bit)Handshake / ISRStatus Register02 / LTSPICE TRANSIENT OSCILLOGRAM (MOSFET TRANSIENT RESPONSE)CH1: V_GS(t) [0V → 12V Gate Pulse]CH2: V_DS(t) [Switching Transient & Flyback Clamping]Timebase: 2.5 µs/divLTspice Simulation Numerical Parameters• Power MOSFET: IRF540N (100V, 33A, R_DS(on) = 44 mΩ)• Rise Time t_r = 35ns | Turn-off Delay t_d(off) = 45ns• Peak Flyback Voltage Clamped by Fast Recovery Diode (UF4007)CIRCUIT TRANSIENT SIMULATION // LTSPICE + 8086 MICROPROCESSOR LAB // VERIFIED SIMULATION MODELSFIRST-PARTY LABORATORY
Layer 1

1. Circuit Topology & Netlists

Power MOSFET switching bridge, freewheeling diode protection, and inductive load modeling.

Layer 2

2. Transient Numerical Simulation

LTspice SPICE engine solving non-linear differential equations across microsecond intervals.

Layer 3

3. Microprocessor Firmware

8086 Assembly source instructions executing on emu8086 simulator for precise hardware timing.

06

Technical Implementation

MOSFET Gate Drive & RC Snubber Simulation

Simulated the gate-source turn-off transient on an N-channel power MOSFET driving an inductive coil, proving that an RC snubber network suppresses ringing below the MOSFET's breakdown rating.

07

Important Algorithms & Decisions

Snubber Damping Resistor Calculation

Rationale: Selected damping resistance based on critical damping criterion R = 2 * sqrt(L / C_parasitic) to eliminate high-frequency parasitic oscillation without excessive steady-state power dissipation.

Trade-off: Dissipates minor energy in the resistor to safeguard semiconductor longevity.

08

Engineering Challenges

Issue: Inductive Voltage Spikes Exceeding Drain-Source Breakdown

Root Cause: Rapid di/dt during MOSFET turn-off induced severe inductive flyback voltage across the coil.

Resolution: Placed a fast-recovery Schottky freewheeling diode in anti-parallel with the load alongside an RC snubber.

09

Testing & Evaluation

SPICE simulation runs evaluating peak Vds, gate rise times, and current transient curves.

Verified Scope: Transient Analysis Waveform Datasets
Peak Vds Voltage
34.2 V (Safe)
Baseline: 98.5 V (Destructive)
Turn-Off Ringing Duration
120 ns
Baseline: 1400 ns
10

Results & Known Limitations

Achieved Results
  • ✓Demonstrated stable switching transient suppression across varying load currents.
  • ✓Verified register-level assembly routines for input/output timing control.
Known Engineering Limitations
  • ⚠SPICE models assume idealized thermal dissipation; physical bench prototyping requires heatsink thermal resistance budgeting.
11

Future Improvements

  • →Integrate closed-loop PWM PID control firmware implemented in C on an STM32 ARM Cortex-M microcontroller.
12

Repository & Verification

Public Repository · GitHub
Active Git Branch
main
Verification Status
Audited & Test Verified

Public repository on GitHub containing SPICE simulation models and assembly firmware.

← All Featured ProjectsExplore Project Archive →